🔬 TIFR Project Engineer Recruitment 2026
Project Engineer – CMS Experiment at CERN Project
Department of High Energy Physics, TIFR Mumbai
📌 TIFR Project Engineer Recruitment 2026 – Overview
This is a temporary project appointment for the CMS experiment project at TIFR Mumbai. It is not a permanent regular TIFR post. The appointment is initially for one year and may be extended for a maximum period of another two years based on performance. The official notice states that the appointment is temporary and non-pensionable and that the candidate will have no claim for permanent or temporary appointment in the Institute during or after the project period.
🔬 Project & Department Details
Applications are invited for one position of Project Engineer to work for the project:
Principal Investigators: Dr. Rajdeep Mohan Chatterjee & Dr. Shilpi Jain
Department: Department of High Energy Physics
Institute: Tata Institute of Fundamental Research (TIFR), Mumbai
📋 TIFR Project Engineer Vacancy Details
| Particular | Details |
|---|---|
| Advertisement Number | 2026/26 |
| Post Name | Project Engineer |
| Total Vacancy | 1 Position |
| Department | Department of High Energy Physics |
| Project | Indian participation in the CMS experiment at CERN: Maintenance, Operation and Upgradation 2020-2025 |
| Monthly Fellowship | ₹60,000/- |
| Age Limit | 29 years as on the closing date of application |
| Nature of Post | Temporary Project Appointment |
| Initial Period | 1 Year |
| Extension | Maximum another 2 years based on performance |
| Selection Method | Personal Interview |
| Application Mode | |
| Last Date | 30 September 2026 |
🎓 Educational Qualification
- B.E. / B.Tech. in Electronics and Communication Engineering or Electronics & (Tele)Communications Engineering.
- Minimum 60% aggregate marks.
- At least 1 year of hands-on experience in designing and debugging high-speed analog, digital and VLSI circuits.
⭐ Desirable Experience / Skills
🛠️ Job Requirements & Responsibilities
- Design, simulate and debug low-noise analog front-end circuits for particle detector readout systems.
- Develop and validate high-speed digital and VLSI systems using CPLDs and FPGAs.
- Write and maintain firmware in hardware description languages including Verilog / Vivado.
- Implement and test high-speed data links for detector data acquisition.
- Program soft processors embedded in FPGA-based readout systems.
- Collaborate with physicists and engineers on end-to-end PCB design and bring-up.
- Support CMS detector operations and on-call hardware maintenance.
💻 Technical Skills Mentioned in Notification
Low-noise amplifiers, ADCs and power management.
FPGA/CPLD synthesis, timing closure and simulation.
Verilog / VHDL; familiarity with Vivado or Quartus toolchains.
LVDS, GbE, PCIe or comparable serial links.
Tools such as Altium and KiCad and mixed-signal board bring-up.
💰 Salary / Fellowship Details
🎁 Job Benefits & Professional Exposure
- 💰 Monthly fellowship of ₹60,000.
- 🔬 Opportunity to work in the Department of High Energy Physics.
- ⚛️ Project work associated with the CMS experiment at CERN.
- 💻 Practical exposure to analog, digital and VLSI electronics.
- 🧪 Experience involving particle-detector readout systems.
- 🔧 Exposure to FPGA/CPLD, PCB design, firmware and high-speed interfaces.
- 🤝 Collaboration with physicists and engineers on detector electronics.
📈 Promotion / Career Growth
This is a project-based temporary appointment, so there is no regular promotion hierarchy or permanent service-cadre promotion mentioned in Advertisement No. 2026/26.
The official notice allows the initial one-year appointment to be extended for a maximum period of another two years based on performance.
🎂 Age Limit
The official Advertisement No. 2026/26 should be checked for any specific applicable age-relaxation provision. No additional age relaxation has been assumed in this article because it is not stated in the supplied notice.
📍 Posting / Work Location
1, Homi Bhabha Road,
Colaba, Mumbai – 400005,
Maharashtra, India.
The Project Engineer position is under the Department of High Energy Physics, TIFR Mumbai.
🎤 Selection Process
The official advertisement explicitly mentions Personal Interview as the method of selection.
There is no written examination mentioned in this advertisement. Candidates should therefore prepare for a technical/personal interview based on their qualification, experience and the requirements of the project.
📝 Step-by-Step Selection Process
Confirm B.E./B.Tech qualification, minimum 60% aggregate, relevant branch and at least one year of specified hands-on experience.
Prepare the CV strictly according to the format prescribed in the official notice.
Attach copies of relevant certificates and a brief statement describing relevant experience.
Include the requested SSC, HSC and B.E./B.Tech academic information.
Provide names, email addresses and contact numbers of two referees.
Email the application to both official contacts given in the notification.
Use: Application for Project Engineer (Name of the candidate)
Ensure the application reaches the concerned email addresses on or before 30 September 2026.
Keep checking the email/contact details supplied in the application for communication from TIFR.
Shortlisted/eligible candidates should follow the interview instructions communicated by TIFR.
📧 How to Apply – Complete Guide
The official TIFR notice instructs interested candidates to send a detailed CV along with copies of relevant certificates and a brief statement of relevant experience to the listed contacts.
Step 1 – Prepare Personal Information
Your CV should contain:
- Name
- Address
- Birthdate
- Nationality
- Contact Number
- Email Address
Step 2 – Add Degree Certificate / Final Marksheet
Attach your final marksheet and/or degree certificate for the eligible degree.
Step 3 – Add Academic History
The prescribed CV format asks candidates to provide academic history for SSC, HSC and B.E./B.Tech.
| Degree / Test | Year | University / Agency | Subjects | Marks / Rank / Score | Remarks |
|---|---|---|---|---|---|
| S.S.C. | Enter Year | Enter Details | Enter Details | Enter Details | Enter Details |
| H.S.C. | Enter Year | Enter Details | Enter Details | Enter Details | Enter Details |
| B.E. / B.Tech. | Enter Year | Enter Details | Enter Details | Enter Details | Enter Details |
Step 4 – Provide Two Referees
Provide the names, email addresses and contact numbers of two referees.
Step 5 – Add Relevant Experience Statement
Include a brief statement explaining your relevant experience, particularly experience related to high-speed analog, digital and VLSI circuits, PCB design, FPGA/CPLD, firmware or other project-relevant skills.
Step 6 – Do Not Add Extra CV Pages
Step 7 – Send Application by Email
Send the application to:
Email: rajdeep.chatterjee@tifr.res.in
Dr. Shilpi Jain
Email: shilpi.jain@tifr.res.in
Step 8 – Use the Correct Email Subject
Step 9 – Submit Before Last Date
The last date for receipt of applications is 30 September 2026.
📂 Required Documents Checklist
- ✅ Detailed CV in the prescribed format.
- ✅ Copies of relevant educational certificates.
- ✅ Final marksheet and/or degree certificate of eligible degree.
- ✅ Academic history for SSC, HSC and B.E./B.Tech.
- ✅ Brief statement of relevant experience.
- ✅ Names, email addresses and contact numbers of two referees.
💳 Application Fee
Do not assume a ₹500 fee or any SC/ST/Women fee exemption. The official notification supplied for this recruitment does not specify such an application fee. Candidates should verify any later official instruction directly with TIFR.
📅 Important Dates
| Event | Date |
|---|---|
| Advertisement Number | 2026/26 |
| Application Last Date | 30 September 2026 |
| Application Mode | |
| Selection | Personal Interview |
⚠️ Important Instructions
- Verify your degree branch before applying.
- Ensure minimum 60% aggregate marks.
- Ensure you have at least one year of relevant hands-on experience.
- Use the prescribed CV format.
- Do not add unnecessary pages/information to the CV.
- Provide two referees as requested.
- Use the exact email subject format.
- Send the application to both listed official email addresses.
- Apply before 30 September 2026.
- Keep copies of the submitted application and email for your records.
🎨 Social Media Job Notification Poster
PROJECT ENGINEER
B.E. / B.Tech.
Minimum 60%
Age 29 Years
Electronics / VLSI
Personal Interview
30 Sept 2026
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🔗 Important Official Links
❓ Frequently Asked Questions
What is the TIFR Project Engineer vacancy?
What is the salary/fellowship?
What is the educational qualification?
What is the age limit?
Is this a permanent TIFR job?
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🚨 Fraud Warning
- ❌ Do not pay unofficial agents for selection.
- ❌ Do not share OTPs or passwords with anyone.
- ❌ Do not trust fake appointment letters.
- ❌ Do not pay anyone promising guaranteed selection.
- ✅ Verify recruitment information directly from the official TIFR website.
- ✅ Use only the official email addresses and notification for application.
- ✅ Verify any subsequent corrigendum or change directly with TIFR.